Xilinx SP601 User Manual

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Summary of Contents

Page 1 - User Guide

[Guide Subtitle] [optional]UG518 (v1.1) August 19, 2009 [optional]SP601 Hardware User Guide UG518 (v1.1) August 19, 2009

Page 2

10 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Chapter 1: SP601 Evaluation BoardFeaturesThe SP601 board provides the following

Page 3 - Revision History

SP601 Hardware User Guide www.xilinx.com 11UG518 (v1.1) August 19, 2009Related Xilinx DocumentsBlock DiagramFigure 1-1 shows a high-level block diagra

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12 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Chapter 1: SP601 Evaluation BoardDetailed DescriptionFigure 1-2 shows a board p

Page 5 - Table of Contents

SP601 Hardware User Guide www.xilinx.com 13UG518 (v1.1) August 19, 2009Detailed Description1. Spartan-6 XC6SLX16-2CSG324 FPGAA Xilinx Spartan-6 XC6SLX

Page 6 - Appendix D: SP601 Master UCF

14 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Chapter 1: SP601 Evaluation BoardReferencesSee the Xilinx Spartan-6 FPGA docume

Page 7 - About This Guide

SP601 Hardware User Guide www.xilinx.com 15UG518 (v1.1) August 19, 2009Detailed DescriptionTable 1-5 shows the connections and pin numbers for the DDR

Page 8 - Online Document

16 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Chapter 1: SP601 Evaluation BoardFigure 1-3 provides the user constraints file

Page 9 - SP601 Evaluation Board

SP601 Hardware User Guide www.xilinx.com 17UG518 (v1.1) August 19, 2009Detailed DescriptionFigure 1-4 provides the UCF constraints for the DDR2 SDRAM

Page 10 - Features

18 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Chapter 1: SP601 Evaluation Board3. SPI x4 FlashThe Xilinx Spartan-6 FPGA hosts

Page 11 - Related Xilinx Documents

SP601 Hardware User Guide www.xilinx.com 19UG518 (v1.1) August 19, 2009Detailed DescriptionX-Ref Target - Figure 1-7Figure 1-7: SPI Flash Interface To

Page 12 - Detailed Description

SP601 Hardware User Guide www.xilinx.com UG518 (v1.1) August 19, 2009Xilinx is disclosing this user guide, manual, release note, and/or specification

Page 13 - I/O Voltage Rails

20 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Chapter 1: SP601 Evaluation BoardFigure 1-8 provides the UCF constraints for th

Page 14 - References

SP601 Hardware User Guide www.xilinx.com 21UG518 (v1.1) August 19, 2009Detailed DescriptionH16 FLASH_A6 23 A6H15 FLASH_A7 22 A7H14 FLASH_A8 20 A8H13 F

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22 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Chapter 1: SP601 Evaluation BoardNote: Memory U10 pin 56 address A24 is not con

Page 16 - X-Ref Target - Figure 1-3

SP601 Hardware User Guide www.xilinx.com 23UG518 (v1.1) August 19, 2009Detailed Description5. 10/100/1000 Tri-Speed Ethernet PHYThe SP601 uses the onb

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24 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Chapter 1: SP601 Evaluation BoardP18 PHY_RXD7 120A9 PHY_TXC_GTXCLK 14B9 PHY_TXC

Page 18 - 3. SPI x4 Flash

SP601 Hardware User Guide www.xilinx.com 25UG518 (v1.1) August 19, 2009Detailed DescriptionReferencesSee the Marvell Alaska Gigabit Ethernet Transceiv

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26 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Chapter 1: SP601 Evaluation BoardReferencesTechnical information on the Silicon

Page 20 - 4. Linear Flash BPI

SP601 Hardware User Guide www.xilinx.com 27UG518 (v1.1) August 19, 2009Detailed Description8-Kb NV MemoryThe SP601 hosts a 8-Kb ST Microelectronics M2

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28 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Chapter 1: SP601 Evaluation BoardOscillator Socket (Single-Ended, 2.5V or 3.3V)

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SP601 Hardware User Guide www.xilinx.com 29UG518 (v1.1) August 19, 2009Detailed DescriptionTable 1-13: LPC PinoutKJ H G FE D C BA1NC NC VREF_A_M2C GND

Page 23 - UG518 (v1.1) August 19, 2009

UG518 (v1.1) August 19, 2009 www.xilinx.com SP601 Hardware User GuideRevision HistoryThe following table shows the revision history for this document.

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30 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Chapter 1: SP601 Evaluation Board34 NC NC LA30_P LA31_N NC NC TRST_L GA0 NC NC3

Page 25 - 6. USB-to-UART Bridge

SP601 Hardware User Guide www.xilinx.com 31UG518 (v1.1) August 19, 2009Detailed DescriptionX-Ref Target - Figure 1-18NET "FMC_CLK0_M2C_N"

Page 26 - 7. IIC Bus

32 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Chapter 1: SP601 Evaluation Board10. Status LEDsTable 1-14 defines the status L

Page 27 - 8. Clock Generation

SP601 Hardware User Guide www.xilinx.com 33UG518 (v1.1) August 19, 2009Detailed Description11. FPGA Awake LED and Suspend JumperThe suspend mode jumpe

Page 28 - SMA Connectors (Differential)

34 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Chapter 1: SP601 Evaluation Board12. FPGA INIT and DONE LEDsThe typical Xilinx

Page 29 - Table 1-13: LPC Pinout

SP601 Hardware User Guide www.xilinx.com 35UG518 (v1.1) August 19, 2009Detailed Description13. User I/OThe SP601 provides the following user and gener

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36 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Chapter 1: SP601 Evaluation BoardUser DIP switchThe SP601 includes an active hi

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SP601 Hardware User Guide www.xilinx.com 37UG518 (v1.1) August 19, 2009Detailed DescriptionUser Pushbutton SwitchesThe SP601 provides five active high

Page 32 - 10. Status LEDs

38 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Chapter 1: SP601 Evaluation BoardGPIO Male Pin HeaderThe SP601 provides a 2X6 G

Page 33

SP601 Hardware User Guide www.xilinx.com 39UG518 (v1.1) August 19, 2009Detailed DescriptionX-Ref Target - Figure 1-27NET "GPIO_LED_0"

Page 34 - 12. FPGA INIT and DONE LEDs

SP601 Hardware User Guide www.xilinx.com UG518 (v1.1) August 19, 2009

Page 35 - 13. User I/O

40 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Chapter 1: SP601 Evaluation Board14. FPGA_PROG_B Pushbutton SwitchThe SP601 pro

Page 36 - User DIP switch

SP601 Hardware User Guide www.xilinx.com 41UG518 (v1.1) August 19, 2009Power ManagementThe SP601 uses power solutions from LTC. An estimate of the cur

Page 37 - User Pushbutton Switches

42 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Chapter 1: SP601 Evaluation BoardConfiguration OptionsThe FPGA on the SP601 Eva

Page 38 - GPIO Male Pin Header

SP601 Hardware User Guide www.xilinx.com 43UG518 (v1.1) August 19, 2009Configuration OptionsThe JTAG chain can be used to program the FPGA and access

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44 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Chapter 1: SP601 Evaluation Board

Page 40 - Power Management

SP601 Hardware User Guide www.xilinx.com 45UG518 (v1.1) August 19, 2009Appendix AReferencesThis section provides references to documentation supportin

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46 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Appendix A: References

Page 42 - Configuration Options

SP601 Hardware User Guide www.xilinx.com 47UG518 (v1.1) August 19, 2009Appendix BDefault Jumper and Switch SettingsTable B-1 shows the default jumper

Page 43

48 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Appendix B: Default Jumper and Switch Settings

Page 44

SP601 Hardware User Guide www.xilinx.com 49UG518 (v1.1) August 19, 2009Appendix CVITA 57.1 FMC ConnectionsTable C-1 shows the VITA 57.1 FMC LPC connec

Page 45

SP601 Hardware User Guide www.xilinx.com 5UG518 (v1.1) August 19, 2009Preface: About This GuideGuide Contents . . . . . . . . . . . . . . . . . . . .

Page 46 - Appendix A: References

50 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Appendix C: VITA 57.1 FMC ConnectionsG13 FMC_LA08_N E11 H13 FMC_LA07_P E7G15 FM

Page 47 - Appendix B

SP601 Hardware User Guide www.xilinx.com 51UG518 (v1.1) August 19, 2009Appendix DSP601 Master UCFThe UCF template is provided for designs that target

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52 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Appendix D: SP601 Master UCFNET "DDR2_LDQS_P" LOC =

Page 49 - VITA 57.1 FMC Connections

SP601 Hardware User Guide www.xilinx.com 53UG518 (v1.1) August 19, 2009NET "FMC_LA07_P" LOC = "E7";NET "FM

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54 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Appendix D: SP601 Master UCFNET "FPGA_CMP_MOSI" LOC =

Page 51 - SP601 Master UCF

SP601 Hardware User Guide www.xilinx.com 55UG518 (v1.1) August 19, 2009NET "PHY_TXCTL_TXEN" LOC = "B8";NET "PH

Page 52 - Appendix D: SP601 Master UCF

6 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Appendix A: ReferencesAppendix B: Default Jumper and Switch SettingsAppendix C

Page 53

SP601 Hardware User Guide www.xilinx.com 7UG518 (v1.1) August 19, 2009PrefaceAbout This GuideThis manual accompanies the Spartan®-6 FPGA SP601 Evaluat

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8 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Preface: About This GuideOnline DocumentThe following conventions are used in th

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SP601 Hardware User Guide www.xilinx.com 9UG518 (v1.1) August 19, 2009Chapter 1SP601 Evaluation BoardOverviewThe SP601 board enables hardware and soft

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