Xilinx ML605 User Manual

User Guide [optional]UG534 (v1.2.1) January 21, 2010 [optional]ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010

10 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation BoardBlock DiagramFigure 1-1 shows a high-level

ML605 Hardware User Guide www.xilinx.com 11UG534 (v1.2.1) January 21, 2010Detailed DescriptionDetailed DescriptionFigure 1-2 shows a board photo with

12 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation Board7Clock generation200 MHz OSC, oscillator s

ML605 Hardware User Guide www.xilinx.com 13UG534 (v1.2.1) January 21, 2010Detailed Description1. Virtex-6 XC6VLX240T-1FFG1156 FPGAA Virtex-6 XC6VLX24

14 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation BoardThe ML605 supports Master BPI-Up, JTAG, an

ML605 Hardware User Guide www.xilinx.com 15UG534 (v1.2.1) January 21, 2010Detailed DescriptionReferencesSee the Xilinx Virtex-6 FPGA documentation fo

16 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation BoardA15 DDR3_A6 90 A6B15 DDR3_A7 86 A7G15 DDR3

ML605 Hardware User Guide www.xilinx.com 17UG534 (v1.2.1) January 21, 2010Detailed DescriptionG12 DDR3_D20 40 DQ20G13 DDR3_D21 42 DQ21F14 DDR3_D22 50

18 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation BoardE24 DDR3_D54 174 DQ54G25 DDR3_D55 176 DQ55

ML605 Hardware User Guide www.xilinx.com 19UG534 (v1.2.1) January 21, 2010Detailed DescriptionThe Memory Interface Generator (MIG) tool guidelines sp

ML605 Hardware User Guide www.xilinx.com UG534 (v1.2.1) January 21, 2010Xilinx is disclosing this user guide, manual, release note, and/or specificat

20 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation Board3. 128 Mb Platform Flash XLA 128 Mb Xilinx

ML605 Hardware User Guide www.xilinx.com 21UG534 (v1.2.1) January 21, 2010Detailed DescriptionML605 Flash Boot OptionsThe ML605 has two parallel wire

22 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation BoardAF24 FLASH_D0 34 DQ0 F2 DQ00AF25 FLASH_D1

ML605 Hardware User Guide www.xilinx.com 23UG534 (v1.2.1) January 21, 2010Detailed DescriptionFPGA Design Considerations for the Configuration FlashA

24 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation Board5. System ACE CF and CompactFlash Connecto

ML605 Hardware User Guide www.xilinx.com 25UG534 (v1.2.1) January 21, 2010Detailed DescriptionTable 1-6 lists the System ACE CF connections.Reference

26 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation Board6. USB JTAGJTAG configuration is provided

ML605 Hardware User Guide www.xilinx.com 27UG534 (v1.2.1) January 21, 2010Detailed DescriptionThe JTAG chain can be used to program the FPGA and acce

28 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation BoardX-Ref Target - Figure 1-7Figure 1-7: ML605

ML605 Hardware User Guide www.xilinx.com 29UG534 (v1.2.1) January 21, 2010Detailed DescriptionSMA Connectors (Differential)A high-precision clock sig

ML605 Hardware User Guide www.xilinx.com 3UG534 (v1.2.1) January 21, 2010Preface: About This GuideGuide Contents . . . . . . . . . . . . . . . . . .

30 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation BoardGTX SMA ClockThe ML605 includes a pair of

ML605 Hardware User Guide www.xilinx.com 31UG534 (v1.2.1) January 21, 2010Detailed Description8. Multi-Gigabit Transceivers (GTX MGTs)The ML605 provi

32 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation Board9. PCI Express Endpoint ConnectivityThe 8-

ML605 Hardware User Guide www.xilinx.com 33UG534 (v1.2.1) January 21, 2010Detailed DescriptionTable 1-8 shows the PCIe connector (P1) that provides u

34 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation BoardThe PCIe interface obtains its power from

ML605 Hardware User Guide www.xilinx.com 35UG534 (v1.2.1) January 21, 2010Detailed DescriptionReferencesSee the following websites for more Virtex-6

36 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation Board11. 10/100/1000 Tri-Speed Ethernet PHYThe

ML605 Hardware User Guide www.xilinx.com 37UG534 (v1.2.1) January 21, 2010Detailed DescriptionSGMII GTX Transceiver Clock GenerationAn Integrated Cir

38 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation BoardReferencesSee the Marvell Alaska Gigabit E

ML605 Hardware User Guide www.xilinx.com 39UG534 (v1.2.1) January 21, 2010Detailed Description12. USB-to-UART BridgeThe ML605 contains a Silicon Labs

4 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010FPGA_PROG_B Pushbutton SW4 (Active-Low). . . . . . . . . . . . . . . . . . .

40 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation Board13. USB ControllerThe ML605 provides USB s

ML605 Hardware User Guide www.xilinx.com 41UG534 (v1.2.1) January 21, 2010Detailed Description14. DVI CodecThe ML605 features a DVI connector (P3) to

42 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation Board15. IIC BusThe ML605 implements four IIC b

ML605 Hardware User Guide www.xilinx.com 43UG534 (v1.2.1) January 21, 2010Detailed DescriptionX-Ref Target - Figure 1-14Figure 1-14: IIC Bus Topology

44 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation Board8 Kb NV MemoryThe ML605 hosts an 8 Kb ST M

ML605 Hardware User Guide www.xilinx.com 45UG534 (v1.2.1) January 21, 2010Detailed Description16. Status LEDsTable 1-19 defines the status LEDs. Tabl

46 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation BoardEthernet PHY Status LEDsThe Ethernet PHY s

ML605 Hardware User Guide www.xilinx.com 47UG534 (v1.2.1) January 21, 2010Detailed DescriptionFPGA INIT and DONE LEDsThe typical Xilinx FPGA power up

48 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation BoardUser LEDsThe ML605 provides two groups of

ML605 Hardware User Guide www.xilinx.com 49UG534 (v1.2.1) January 21, 2010Detailed DescriptionUser Pushbutton SwitchesThe ML605 provides six active-H

ML605 Hardware User Guide www.xilinx.com 5UG534 (v1.2.1) January 21, 2010PrefaceAbout This GuideThis manual accompanies the Virtex®-6 FPGA ML605 Eval

50 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation BoardUser DIP SwitchThe ML605 includes an activ

ML605 Hardware User Guide www.xilinx.com 51UG534 (v1.2.1) January 21, 2010Detailed DescriptionUser SMA GPIOThe ML605 includes an pair of SMA connecto

52 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation BoardLCD Display (16 Character x 2 Lines)The ML

ML605 Hardware User Guide www.xilinx.com 53UG534 (v1.2.1) January 21, 2010Detailed Description18. Switches The ML605 Evaluation board includes the fo

54 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation BoardFPGA_PROG_B Pushbutton SW4 (Active-Low)Thi

ML605 Hardware User Guide www.xilinx.com 55UG534 (v1.2.1) January 21, 2010Detailed DescriptionSystem ACE CF CompactFlash Image Select DIP Switch S1Sy

56 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation BoardMode, Osc Enable, Boot EEPROM Select, and

ML605 Hardware User Guide www.xilinx.com 57UG534 (v1.2.1) January 21, 2010Detailed DescriptionSee “3. 128 Mb Platform Flash XL,” page 20 and “4. 32 M

58 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation BoardNote: The ML605 board VADJ voltage for the

ML605 Hardware User Guide www.xilinx.com 59UG534 (v1.2.1) January 21, 2010Detailed DescriptionC14 FMC_HPC_LA10_P AM20 D14 FMC_HPC_LA09_P AM18C15 FMC_

6 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Preface: About This Guide• Virtex-6 FPGA Memory Resources User GuideThe func

60 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation BoardE28 FMC_HPC_HB09_N AK34 F28 FMC_HPC_HB08_P

ML605 Hardware User Guide www.xilinx.com 61UG534 (v1.2.1) January 21, 2010Detailed DescriptionJ2 FMC_HPC_CLK3_M2C_P(2)U84.6 K4 FMC_HPC_CLK2_M2C_P(2)U

62 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation BoardTable 1-29: Power Supply Voltages for HPC

ML605 Hardware User Guide www.xilinx.com 63UG534 (v1.2.1) January 21, 2010Detailed Description20. VITA 57.1 FMC LPC ConnectorThe ML605 implements bot

64 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation BoardTable 1-30 shows the VITA 57.1 FMC LPC con

ML605 Hardware User Guide www.xilinx.com 65UG534 (v1.2.1) January 21, 2010Detailed DescriptionReferencesSee the data sheet for the ROHS compliant FMC

66 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation BoardOnboard Power RegulationFigure 1-28 shows

ML605 Hardware User Guide www.xilinx.com 67UG534 (v1.2.1) January 21, 2010Detailed DescriptionVoltage and current monitoring and control are availabl

68 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation Board22. System MonitorThe System Monitor provi

ML605 Hardware User Guide www.xilinx.com 69UG534 (v1.2.1) January 21, 2010Detailed DescriptionSystem Monitor Header (J35)Figure 1-30 shows the pinout

ML605 Hardware User Guide www.xilinx.com 7UG534 (v1.2.1) January 21, 2010Chapter 1ML605 Evaluation BoardOverviewThe ML605 board enables hardware and

70 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation BoardML605 Board Power MonitorIn addition to mo

ML605 Hardware User Guide www.xilinx.com 71UG534 (v1.2.1) January 21, 2010Detailed DescriptionFan ControllerIn highly demanding situations, active th

72 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation BoardFPGA Power Supply MarginingThe PMBus (IIC)

ML605 Hardware User Guide www.xilinx.com 73UG534 (v1.2.1) January 21, 2010Configuration OptionsConfiguration OptionsThe FPGA on the ML605 Evaluation

74 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation Board

ML605 Hardware User Guide www.xilinx.com 75UG534 (v1.2.1) January 21, 2010Appendix ADefault Switch and Jumper SettingsTabl e A - 1 : Default Switch

76 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Appendix A: Default Switch and Jumper SettingsTabl e A - 2 : Default Jumpe

ML605 Hardware User Guide www.xilinx.com 77UG534 (v1.2.1) January 21, 2010Appendix BVITA 57.1 FMC LPC (J63) and HPC (J64) Connector PinoutFigure B-1

78 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Appendix B: VITA 57.1 FMC LPC (J63) and HPC (J64) Connector PinoutFigure B-

ML605 Hardware User Guide www.xilinx.com 79UG534 (v1.2.1) January 21, 2010Appendix CML605 Master UCFThe UCF template is provided for designs that tar

8 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation BoardFeaturesThe ML605 provides the following fe

80 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Appendix C: ML605 Master UCFNET "DDR3_D8" L

ML605 Hardware User Guide www.xilinx.com 81UG534 (v1.2.1) January 21, 2010NET "DDR3_DQS0_P" LOC = "D12"; ##

82 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Appendix C: ML605 Master UCFNET "FLASH_A21" L

ML605 Hardware User Guide www.xilinx.com 83UG534 (v1.2.1) January 21, 2010NET "FMC_HPC_DP6_M2C_N" LOC = "AM6"; ##

84 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Appendix C: ML605 Master UCFNET "FMC_HPC_HB03_P" L

ML605 Hardware User Guide www.xilinx.com 85UG534 (v1.2.1) January 21, 2010NET "FMC_HPC_LA16_N" LOC = "AN23"; ##

86 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Appendix C: ML605 Master UCFNET "FMC_LPC_LA07_N" L

ML605 Hardware User Guide www.xilinx.com 87UG534 (v1.2.1) January 21, 2010NET "FPGA_M0" LOC = "U8"; ##

88 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Appendix C: ML605 Master UCFNET "PCIE_RX2_N" L

ML605 Hardware User Guide www.xilinx.com 89UG534 (v1.2.1) January 21, 2010NET "PMBUS_DATA_LS" LOC = "AB10"; ##

ML605 Hardware User Guide www.xilinx.com 9UG534 (v1.2.1) January 21, 2010Overview• 16. Status LEDs♦ Ethernet status♦ FPGA INIT♦ FPGA DONE♦ System ACE

90 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Appendix C: ML605 Master UCFNET "USB_D6_LS" L

ML605 Hardware User Guide www.xilinx.com 91UG534 (v1.2.1) January 21, 2010Appendix DReferencesThis section provides references to documentation suppo

92 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Appendix D: ReferencesAdditional documentation:22. Micron Technology, Inc.,