Xilinx SP601 User Manual download pdf (Page 28)

28 www.xilinx.com SP601 Hardware User Guide

UG518 (v1.1) August 19, 2009

Chapter 1: SP601 Evaluation Board

Oscillator Socket (Single-Ended, 2.5V or 3.3V)

One populated single-ended clock socket (X2) is provided for user applications. The option

of 3.3V or 2.5V power may be selected via a 0 ohm resistor selection. The SP601 board is

shipped with a 27MHz 2.5V oscillator installed.

SMA Connectors (Differential)

A high-precision clock signal can be provided to the FPGA using differential clock signals

through the onboard 50-ohm SMA connectors J7(P)/J8(N).

9. VITA 57.1 FMC-LPC Connector

The VITA 57.1 FMC expansion connector (J1) on the SP601 implements the VITA 57.1.1 LPC

format of the VITA 57.1 FMC standard specification. The VITA 57.1 FMC-LPC connector

provides 68 single-ended (34 differential) user-defined signals (Table 1-13). The VITA 57.1

FMC standard calls for two connector densities: a High Pin Count (HPC) and a Low Pin

Count (LPC) implementation. A common 10 x 40 position (400 pin locations) connector

form factor is used for both versions. The HPC version has 400 pins present, the LPC

version, 160 pins. The Samtec connector system is rated for signaling speeds up to 9 GHz

(18 Gb/s) based on a -3dB insertion loss point within a two-level signaling environment.

Refer to the Samtec website

for data sheets and characterization information for the RoHS-

compliant VITA 57.1 FMC-LPC connector (ASP-134603-01) and its mate.

Note that the SP601 board FMC-LPC connector J1 VADJ voltage is FIXED at 2.5V (non-

adjustable). This rail cannot be turned off. The SP601 VITA 57.1 FMC interface is

compatible with 2.5V Mezzanine Cards capable of supporting 2.5V VADJ.

The SP601 supports all FMC LA Bus connections available on the FMC LPC connector,

(LA[00:33]) along with all available FMC M2C clock pairs (CLK0_M2C_P/N and

CLK1_M2C_P/N). The SP601 does not support the FMC DP Bus connections since the

SP601 does not support any Gigabit Transceivers on the FMC DP Bus. Therefore,

DP0_C2M_P/N, DP0_M2C_P/N and GBTCLK0_M2C_P/N are not supported by the

SP601 FMC interface.

For more details about FMC, see the VITA57.1 specification available at

http://www.vita.com/fmc.html

X-Ref Target - Figure 1-16

NET "USER_CLOCK" LOC = "V10";

Figure 1-16: UCF Location Constraints for Oscillator Socket Connections

X-Ref Target - Figure 1-17

NET "SMACLK_N" LOC = "H18";

NET "SMACLK_P" LOC = "H17";

Figure 1-17: UCF Location Constraints for SMA Connectors Connections

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Xilinx SP601 User Manual Page 28