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102 www.xilinx.com Virtex-5 FPGA ML561 User Guide
UG199 (v1.2) April 19, 2008
Appendix A: FPGA Pinouts
R
DDR2 DIMM Deep Interface (cont.)
DDR2_DIMM_DQ_BY4_B4 V34 DDR2_DIMM_DQ_BY7_B7 Y32
DDR2_DIMM_DQ_BY4_B5 W34 DDR2_DIMM_DQ_CB0_7_B0 D34
DDR2_DIMM_DQ_BY4_B6 V33 DDR2_DIMM_DQ_CB0_7_B1 C34
DDR2_DIMM_DQ_BY4_B7 V32 DDR2_DIMM_DQ_CB0_7_B2 D32
DDR2_DIMM_DQ_BY5_B0 AP32 DDR2_DIMM_DQ_CB0_7_B3 C32
DDR2_DIMM_DQ_BY5_B1 AN32 DDR2_DIMM_DQ_CB0_7_B4 C33
DDR2_DIMM_DQ_BY5_B2 AN33 DDR2_DIMM_DQ_CB0_7_B5 B33
DDR2_DIMM_DQ_BY5_B3 AN34 DDR2_DIMM_DQ_CB0_7_B6 A33
DDR2_DIMM_DQ_BY5_B4 AM32 DDR2_DIMM_DQ_CB0_7_B7 B32
DDR2_DIMM_DQ_BY5_B5 AM33 DDR2_DIMM_DQS_BY0_L_N N30
DDR2_DIMM_DQ_BY5_B6 AL33 DDR2_DIMM_DQS_BY0_L_P M31
DDR2_DIMM_DQ_BY5_B7 AL34 DDR2_DIMM_DQS_BY1_L_N P30
DDR2_DIMM_DQ_BY6_B0 U31 DDR2_DIMM_DQS_BY1_L_P P31
DDR2_DIMM_DQ_BY6_B1 U32 DDR2_DIMM_DQS_BY2_L_N L31
DDR2_DIMM_DQ_BY6_B2 T34 DDR2_DIMM_DQS_BY2_L_P K31
DDR2_DIMM_DQ_BY6_B3 U33 DDR2_DIMM_DQS_BY3_L_N J34
DDR2_DIMM_DQ_BY6_B4 R32 DDR2_DIMM_DQS_BY3_L_P H34
DDR2_DIMM_DQ_BY6_B5 R33 DDR2_DIMM_DQS_BY4_L_N AE34
DDR2_DIMM_DQ_BY6_B6 R34 DDR2_DIMM_DQS_BY4_L_P AF34
DDR2_DIMM_DQ_BY6_B7 T33 DDR2_DIMM_DQS_BY5_L_N AE32
DDR2_DIMM_DQ_BY7_B0 AF33 DDR2_DIMM_DQS_BY5_L_P AD32
DDR2_DIMM_DQ_BY7_B1 AB33 DDR2_DIMM_DQS_BY6_L_N K32
DDR2_DIMM_DQ_BY7_B2 AC33 DDR2_DIMM_DQS_BY6_L_P K33
DDR2_DIMM_DQ_BY7_B3 AB32 DDR2_DIMM_DQS_BY7_L_N AJ34
DDR2_DIMM_DQ_BY7_B4 AC32 DDR2_DIMM_DQS_BY7_L_P AH34
DDR2_DIMM_DQ_BY7_B5 AD34 DDR2_DIMM_DQS_CB0_7_L_N K34
DDR2_DIMM_DQ_BY7_B6 AC34 DDR2_DIMM_DQS_CB0_7_L_P L34
DDR2 DIMM Wide Interface
DDR2_DIMM5_CK0_N AM13 DDR2_DIMM5_CK2_N AP14
DDR2_DIMM5_CK0_P AN13 DDR2_DIMM5_CK2_P AN14
DDR2_DIMM5_CK1_N AA10 DDR2_DIMM5_CKE0 AC10
DDR2_DIMM5_CK1_P AB10 DDR2_DIMM5_CKE1 AM11
Table A-2: FPGA #2 Pinout (Continued)
Signal Name Pin Signal Name Pin
- Virtex-5 FPGA ML561 1
- Memory Interfaces 1
- Development Board 1
- Revision History 2
- Table of Contents 3
- Chapter 6: Configuration 4
- Appendix A: FPGA Pinouts 4
- Appendix C: LCD Interface 5
- About This Guide 7
- Additional Support Resources 8
- Conventions 9
- Terminology 9
- Preface: About This Guide 10
- Introduction 11
- Chapter 1: Introduction 14
- Getting Started 15
- Applying Power to the Board 16
- Hardware Description 17
- DDR400 SDRAM Components 19
- DDR2 DIMM 19
- DDR2 SDRAM Components 20
- QDRII SRAM 20
- RLDRAM II Devices 20
- Memory Details 21
- DDR2 SDRAM DIMM 23
- QDRII and RLDRAM II Memories 25
- External Interfaces 27
- 200 MHz LVPECL Clock 28
- SMA Clock 28
- 33 MHz Clock 28
- GTP Clocks 29
- General-Purpose Headers 29
- DIP Switch 29
- Seven-Segment Displays 30
- Light Emitting Diodes (LEDs) 30
- Pushbuttons 30
- Power On or Off Slide Switch 31
- Soft Touch Probe Points 31
- Power Measurement Header 31
- Power Regulation 33
- Voltage Regulators 34
- Board Design Considerations 36
- Electrical Requirements 39
- Power Consumption 41
- FPGA Internal Power Budget 46
- Chapter 5 47
- Configuration 51
- 1. X = Supported 52
- 2. — = Not applicable 52
- System ACE Interface 53
- Chapter 6: Configuration 54
- ML561 Hardware-Simulation 55
- Correlation 55
- Test Setup 56
- UG199_c7_01_062707 57
- Table 7-3: DIP[1:2] Settings 60
- Voltage (mV) 61
- Time (ps) 61
- (DDR2 Memory Via) 62
- Time (ns) 63
- DDR2 Component Read Operation 65
- Cursor 1: 697.1 mV, 1.2345 ns 66
- Cursor 2: 774.6 mV, 2.5191 ns 66
- UG199_c7_21_071907 70
- UG199_c7_30_071907 76
- QDRII Write Operation 81
- QDRII Read Operation 86
- Summary and Recommendations 91
- FPGA Pinouts 95
- FPGA #1 Pinout 97
- FPGA #2 Pinout 100
- Appendix A: FPGA Pinouts 102
- FPGA #3 Pinout 108
- Bill of Materials 115
- Appendix B: Bill of Materials 116
- UG199 (v1.2) April 19, 2008 117
- LCD Interface 119
- Hardware Schematic Diagram 120
- Peripheral Device KS0713 121
- Controller 122
- LCD Panel 122
- LED Backlight 122
- 128 x 64 DOTS 122
- Controller – Operation 123
- Appendix C: LCD Interface 124
- UG199_C_05_050106 126
- ♦ The LCD bias is set to: 129
- Instruction Set 130
- Design Examples 134
- Display Command Byte 135
- UG199_C_09_050106 136
- Array Connector Numbering 139
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