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46 www.xilinx.com Virtex-5 FPGA ML561 User Guide
UG199 (v1.2) April 19, 2008
Chapter 4: Electrical Requirements
R
FPGA Internal Power Budget
Table 4-4 summarizes power consumption estimates by each of the three
XC5VLX50T-FFG1136 FPGAs on the Virtex-5 FPGA ML561 Development Board. This
estimate derives the FPGA utilization information from the respective map report of a fully
configured reference design.
Table 4-4: ML561 FPGA Power Estimate Summary
FPGA # FPGA #1 FPGA #2
(1)
FPGA #3
Interface
DDR400 Comp
(DCI)
DDR2 Comp
(DCI)
DDR2 DIMM
(DCI)
QDRII (DCI)
RLDRAM II
(DCI)
I/O Standard SSTL_18 HSTL_18 HSTL_18
Total Power (W) 3.7 3.1 10.2 6.3 4.5
V
CCINT
(1.0V) mW 763 763 1945 1160 1515
V
CCAUX
(2.5V) mW 435 544 544 544 544
SSTL_18 V
CCO
(1.8V) mW 1819 7664
SSTL_2 V
CCO
(2.6V) mW 2469
HSTL_18 V
CCO
(1.8V) mW 4571 2406
I/O Frequency (MHz) 200 400 400 400 400
Fabric Frequency (MHz) 200 200 200 200 200
Number of Slices 1500 1500 5910 2750 1951
Number of Flip-flops 2000 2000 7352 2000 1800
Number of Shift Register LUTs 50 50 143 750 400
Number of Block RAMs 5 5 17 14 21
Number of DCMs 2 2 2 2 2
Inputs 10 10 10 90 13
Outputs 50 50 90 160 52
Bidirectionals 36 40 192 0 36
Ambient Temperature (°C) 25 25 25 25 25
Airflow (LFM) 0 0 250 250 0
Heat Sink (Theta-J) n/a n/a 5 5 n/a
Junction Temperature (°C) 67 60 78 58 76
Notes:
1. For DDR2 DIMMs as well as QDRII memory interfaces with DCI, an MD35E-10B heat sink is needed. A heat sink with Theta-J = 5.0
should be okay without airflow. See http://www.alphanovatech.com/c_md35e.html
for the heat sink profile. A heat sink with
Theta-J = 5.0 might need airflow of 250 LFM.
- Virtex-5 FPGA ML561 1
- Memory Interfaces 1
- Development Board 1
- Revision History 2
- Table of Contents 3
- Chapter 6: Configuration 4
- Appendix A: FPGA Pinouts 4
- Appendix C: LCD Interface 5
- About This Guide 7
- Additional Support Resources 8
- Conventions 9
- Terminology 9
- Preface: About This Guide 10
- Introduction 11
- Chapter 1: Introduction 14
- Getting Started 15
- Applying Power to the Board 16
- Hardware Description 17
- DDR400 SDRAM Components 19
- DDR2 DIMM 19
- DDR2 SDRAM Components 20
- QDRII SRAM 20
- RLDRAM II Devices 20
- Memory Details 21
- DDR2 SDRAM DIMM 23
- QDRII and RLDRAM II Memories 25
- External Interfaces 27
- 200 MHz LVPECL Clock 28
- SMA Clock 28
- 33 MHz Clock 28
- GTP Clocks 29
- General-Purpose Headers 29
- DIP Switch 29
- Seven-Segment Displays 30
- Light Emitting Diodes (LEDs) 30
- Pushbuttons 30
- Power On or Off Slide Switch 31
- Soft Touch Probe Points 31
- Power Measurement Header 31
- Power Regulation 33
- Voltage Regulators 34
- Board Design Considerations 36
- Electrical Requirements 39
- Power Consumption 41
- FPGA Internal Power Budget 46
- Chapter 5 47
- Configuration 51
- 1. X = Supported 52
- 2. — = Not applicable 52
- System ACE Interface 53
- Chapter 6: Configuration 54
- ML561 Hardware-Simulation 55
- Correlation 55
- Test Setup 56
- UG199_c7_01_062707 57
- Table 7-3: DIP[1:2] Settings 60
- Voltage (mV) 61
- Time (ps) 61
- (DDR2 Memory Via) 62
- Time (ns) 63
- DDR2 Component Read Operation 65
- Cursor 1: 697.1 mV, 1.2345 ns 66
- Cursor 2: 774.6 mV, 2.5191 ns 66
- UG199_c7_21_071907 70
- UG199_c7_30_071907 76
- QDRII Write Operation 81
- QDRII Read Operation 86
- Summary and Recommendations 91
- FPGA Pinouts 95
- FPGA #1 Pinout 97
- FPGA #2 Pinout 100
- Appendix A: FPGA Pinouts 102
- FPGA #3 Pinout 108
- Bill of Materials 115
- Appendix B: Bill of Materials 116
- UG199 (v1.2) April 19, 2008 117
- LCD Interface 119
- Hardware Schematic Diagram 120
- Peripheral Device KS0713 121
- Controller 122
- LCD Panel 122
- LED Backlight 122
- 128 x 64 DOTS 122
- Controller – Operation 123
- Appendix C: LCD Interface 124
- UG199_C_05_050106 126
- ♦ The LCD bias is set to: 129
- Instruction Set 130
- Design Examples 134
- Display Command Byte 135
- UG199_C_09_050106 136
- Array Connector Numbering 139
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