Xilinx Virtex-5 User Manual Page 27
- Page / 140
- Table of contents
- BOOKMARKS
Rated. / 5. Based on customer reviews
Virtex-5 FPGA ML561 User Guide www.xilinx.com 27
UG199 (v1.2) April 19, 2008
External Interfaces
R
External Interfaces
The external interfaces of the Virtex-5 FPGA ML561 Development Board are described in
this section.
RS-232
The ML561 board provides an RS-232 serial interface using a Maxim MAX3316ECUP
device. The maximum speed of this device is 460 Kbps.
Hooks are provided to connect and disconnect FPGAs to the RS-232 serial interface, by
placing jumpers on headers based on the FPGA involved in the communication. Only one
FPGA is allowed in the communication, and others must be disconnected before operation.
The ML561 toolkit CD contains code to implement a UART core in one FPGA for
interfacing with a host PC.
The RS-232 interface is accessible through a male DB-9 serial connector (P73).
USB
Full-speed (12 Mbps) USB functionality is proved using a Silicon Laboratories CP2102-GM
USB to RS-232 Bridge. RS-232 and USB signals are converted between one another so a
RS-232 core needs to be implemented in the FPGA for communication. A level translator is
used to convert between the 2.5V I/O of the FPGA and the 3.3V I/O the CP2102 uses.
Hooks are provided to connect and disconnect FPGAs to the USB connection, by placing
jumpers on headers based on the FPGA involved in the communication. Only one FPGA is
allowed in the communication, and others must be disconnected before operation.
The USB interface is accessible through a female ‘A’ USB connector (J29).
Clocks
The ML561 board contains a 200 MHz LVPECL clock oscillator and connectors for external
clock inputs for use as system clocks (J19 and J20). The GTP transceivers use their own
clock source that can be provided through SMA connectors on the board (J16 and J21).
Table 3-8: RS-232 Jumper Settings
To Connect FPGA # to
DB-9 (P73)
TX RX
FPGA #1 P52 Pin 2 -> P52 Pin 1 P53 Pin 2 -> P53 Pin 1
FPGA #2 P52 Pin 2 -> P51 Pin 1 P53 Pin 2 -> P54 Pin 1
FPGA #3 P52 Pin 2 -> P52 Pin 3 P53 Pin 2 -> P53 Pin 3
Table 3-9: USB Jumper Settings
To Connect FPGA # to DB-9
(J29)
TX RX
FPGA #1 P36 Pin 2 -> P36 Pin 1 P22 Pin2 -> P22 Pin 1
FPGA #2 P36 Pin 2 -> P35 Pin 1 P22 Pin2 -> P23 Pin 1
FPGA #3 P36 Pin 2 -> P36 Pin 3 P22 Pin2 -> P22 Pin 3
- Virtex-5 FPGA ML561 1
- Memory Interfaces 1
- Development Board 1
- Revision History 2
- Table of Contents 3
- Chapter 6: Configuration 4
- Appendix A: FPGA Pinouts 4
- Appendix C: LCD Interface 5
- About This Guide 7
- Additional Support Resources 8
- Conventions 9
- Terminology 9
- Preface: About This Guide 10
- Introduction 11
- Chapter 1: Introduction 14
- Getting Started 15
- Applying Power to the Board 16
- Hardware Description 17
- DDR400 SDRAM Components 19
- DDR2 DIMM 19
- DDR2 SDRAM Components 20
- QDRII SRAM 20
- RLDRAM II Devices 20
- Memory Details 21
- DDR2 SDRAM DIMM 23
- QDRII and RLDRAM II Memories 25
- External Interfaces 27
- 200 MHz LVPECL Clock 28
- SMA Clock 28
- 33 MHz Clock 28
- GTP Clocks 29
- General-Purpose Headers 29
- DIP Switch 29
- Seven-Segment Displays 30
- Light Emitting Diodes (LEDs) 30
- Pushbuttons 30
- Power On or Off Slide Switch 31
- Soft Touch Probe Points 31
- Power Measurement Header 31
- Power Regulation 33
- Voltage Regulators 34
- Board Design Considerations 36
- Electrical Requirements 39
- Power Consumption 41
- FPGA Internal Power Budget 46
- Chapter 5 47
- Configuration 51
- 1. X = Supported 52
- 2. — = Not applicable 52
- System ACE Interface 53
- Chapter 6: Configuration 54
- ML561 Hardware-Simulation 55
- Correlation 55
- Test Setup 56
- UG199_c7_01_062707 57
- Table 7-3: DIP[1:2] Settings 60
- Voltage (mV) 61
- Time (ps) 61
- (DDR2 Memory Via) 62
- Time (ns) 63
- DDR2 Component Read Operation 65
- Cursor 1: 697.1 mV, 1.2345 ns 66
- Cursor 2: 774.6 mV, 2.5191 ns 66
- UG199_c7_21_071907 70
- UG199_c7_30_071907 76
- QDRII Write Operation 81
- QDRII Read Operation 86
- Summary and Recommendations 91
- FPGA Pinouts 95
- FPGA #1 Pinout 97
- FPGA #2 Pinout 100
- Appendix A: FPGA Pinouts 102
- FPGA #3 Pinout 108
- Bill of Materials 115
- Appendix B: Bill of Materials 116
- UG199 (v1.2) April 19, 2008 117
- LCD Interface 119
- Hardware Schematic Diagram 120
- Peripheral Device KS0713 121
- Controller 122
- LCD Panel 122
- LED Backlight 122
- 128 x 64 DOTS 122
- Controller – Operation 123
- Appendix C: LCD Interface 124
- UG199_C_05_050106 126
- ♦ The LCD bias is set to: 129
- Instruction Set 130
- Design Examples 134
- Display Command Byte 135
- UG199_C_09_050106 136
- Array Connector Numbering 139
Related products and manuals for Unknown Xilinx Virtex-5
Unknown Xilinx SP601 User Manual
(55 pages)
(55 pages)
Unknown Xilinx UG133 User Manual
(18 pages)
(18 pages)
Unknown Xilinx ML403 User Manual
(33 pages)
(33 pages)
Unknown Xilinx DS610 User Manual
(98 pages)
(98 pages)
© 2020, manymanuals.com. All rights reserved. | 2.074 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comments to this Manuals